1. Field of the Invention
The present invention relates to a multiply accumulator (MAC) and, more particularly, to a multiply accumulator for two N bit multipliers and an M bit addend, in which M is larger than 2N. The multiply accumulator according to the present invention achieves a high speed operation by simultaneously performing multiplication and addition.
2. Description of the Related Art
Typically, digital electronic products are equipped with microprocessors for performing logical operations and arithmetical operations with respect to digital signals. The arithmetical operation of the digital signals normally includes a series of multiplications and accumulations (or referred to as additions), which are carried out by means of a multiply accumulator. FIGS. 1(a) and 1(b) are schematic diagrams showing two examples of configurations of conventional multiply accumulators for performing a multiplication-and-addition operation X·Y+A. In this operation, the two multipliers X and Y as well as the addend A are all digital signals consisting of a plurality of bits, such as 16 or 32 bits. Also, the symbol · indicates a multiplication while the symbol + indicates an addition.
Referring to FIG. 1(a), a conventional multiply accumulator 1 includes a carry save adder tree 10 and an adder 11. First, the two multipliers X and Y are input into the carry save adder tree 10 for performing the multiplication X·Y by accumulation of partial products. Typically, the carry save adder tree 10 has a configuration of a plurality of adders (not shown) interconnected as a tree structure for performing the accumulation of the partial products of the multipliers X and Y. After completing the multiplication X·Y, the carry save adder tree 10 outputs a final product into the adder 11 for performing the addition with respect to the addend A. Therefore, the arithmetical multiplication-and-addition operation X·Y+A is completed.
Another conventional multiply accumulator 2 shown in FIG. 1(b) has a configuration different from that shown in FIG. 1(a) in that the conventional multiply accumulator 2 further includes a Booth encoder 12. As shown in FIG. 1(b), the multipliers X and Y are input into the carry save adder tree 10 through the Booth encoder 12′. With the Booth encoder 12, the realization of the multiplication X·Y has become easier in the carry save adder tree 10, thereby raising the overall processing speed of the arithmetical multiplication-and-addition operation X·Y+A.
Along with a growing demand for a microprocessor with a better performance, it is necessary to raise the operating speed of the multiply accumulator employed in the microprocessor. Both of the conventional multiply accumulators 1 and 2 shown in FIGS. 1(a) and 1(b) perform the multiplication and the addition in such two separate steps that the addition does not be carried out until the completion of the multiplication. As a result, the overall operating speed of the conventional multiply accumulators 1 and 2 are inevitably restrained from optimization since the addend remains idle before the addition can be performed.